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| Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. BUK583-60A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. 60 3.2 1.8 150 0.10 UNIT V A W C PINNING - SOT223 PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION PIN CONFIGURATION 4 SYMBOL d g 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 k Tamb = 25 C Tamb = 100 C Tamb = 25 C Tamb = 25 C MIN. - 55 MAX. 60 60 15 3.2 2.0 13 1.8 150 150 UNIT V V V A A A W C C THERMAL RESISTANCES SYMBOL Rth j-sp Rth j-amb PARAMETER From junction to solder point From junction to ambient 1 CONDITIONS Mounted on any PCB Mounted on PCB of fig.18 MIN. - TYP. 12 - MAX. 15 70 UNIT K/W K/W 1 Temperature measured at solder joint on drain tab. September 1995 1 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; VDS = 60 V; VGS = 0 V; Tj = 125 C VGS = 15 V; VDS = 0 V VGS = 5 V; ID = 3.2 A MIN. 60 1.0 - BUK583-60A TYP. 70 1.5 1 0.1 10 0.08 MAX. 2.0 10 1.0 100 0.10 UNIT V V A mA nA DYNAMIC CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time CONDITIONS VDS = 25 V; ID = 3.2 A VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 ; Rgen = 50 MIN. TYP. 6.0 650 240 120 10 35 60 55 MAX. 825 350 160 20 55 90 80 UNIT S pF pF pF ns ns ns ns REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 3.2 A; VGS = 0 V IF = 3.2 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V MIN. TYP. 0.85 70 0.25 MAX. 3.2 13 1.1 UNIT A A V ns C AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 3.2 A; VDD 25 V; VGS = 5 V; RGS = 50 ; Tamb = 25 C MIN. TYP. MAX. 45 UNIT mJ September 1995 2 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK583-60A 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 100 ID / A BUK583-60A 10 RD S (O = N) VD S/ ID tp = 10 us 100 us 1 ms 10 ms DC 100 ms 1s 10 s 1 0.1 0 20 40 60 80 Tamb / C 100 120 140 0.01 0.1 1 10 VDS / V 100 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tamb) ID% Normalised Current Derating Fig.4. Safe operating area Tamb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp ID / A 5.0 9 8 7 6 5 4 3 2 1 2.5 VGS / V = 3.0 4.0 3.5 4.5 120 110 100 90 80 70 60 50 40 30 20 10 0 10 0 20 40 60 80 Tamb / C 100 120 140 0 0 0.5 1 VDS / V 1.5 2 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tamb); conditions: VGS 5 V Zth j-amb / (K/W) BUKX83 Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS RDS(ON) / Ohm VGS / V = 2.5 1 0.8 3 0.6 1E+02 D= 0.5 0.2 0.1 0.05 0.02 P D tp D= tp T 1.2 1E+01 1E+00 0.4 3.5 0.2 0 0 2 4 ID / A 6 8 10 1E-01 0 1E-02 1E-07 1E-05 1E-03 t/s 1E-01 T t 1E+01 1E+03 Fig.3. Transient thermal impedance. Zth j-amb = f(t); parameter D = tp/T Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS September 1995 3 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK583-60A 10 9 8 7 6 5 4 3 ID / A VGS(TO) / V max. 2 typ. min. 1 Tj / C = 150 2 1 0 0 1 2 VGS / V 3 4 5 25 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S 15 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 1E-01 1E-02 10 1E-03 2% typ 98 % 1E-04 5 1E-05 0 0 2 4 ID / A 6 8 10 1E-06 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V a Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS C / pF Normalised RDS(ON) = f(Tj) 10000 BUK5y3-50 1.5 1000 1.0 Ciss Coss 0.5 100 Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 10 0 20 VDS / V 40 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 3.2 A; VGS = 5 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz September 1995 4 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK583-60A 10 9 8 7 6 5 4 3 2 1 0 VGS / V 120 110 100 90 80 VDS / V =12 48 WDSS% Normalised Avalanche Energy 70 60 50 40 30 20 10 0 0 5 QG / nC 10 15 20 40 60 80 100 Tamb/ C 120 140 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 3.2 A; parameter VDS ID / A 10 9 8 7 6 5 4 3 2 1 0 0 0.5 VGS / V 1 1.5 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tamb); conditions: ID = 3.2 A + L VDS VGS Tj / C = 150 25 VDD -ID/100 T.U.T. R 01 shunt 0 RGS Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) September 1995 5 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET MOUNTING INSTRUCTIONS Dimensions in mm. 3.8 min BUK583-60A PRINTED CIRCUIT BOARD Dimensions in mm. 36 1.5 min 18 60 9 2.3 1.5 min (3x) 6.3 4.6 4.5 10 1.5 min 4.6 7 15 50 Fig.17. soldering pattern for surface mounting SOT223. Fig.18. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick). September 1995 6 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 0.11 g 0.32 0.24 6.7 6.3 3.1 2.9 B BUK583-60A 0.2 M A 4 A 0.10 0.02 3.7 3.3 13 7.3 6.7 16 max 1 10 max 1.8 max 1.05 0.85 4.6 2.3 2 0.80 0.60 3 0.1 M (4x) B Fig.19. SOT223 surface mounting package. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8". September 1995 7 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK583-60A This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1995 8 Rev 1.200 |
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